Various techniques have been investigated and used for metallizing semiconductor chips. These methods include the lift-off process, thru-mask methods, metal RIE and metal and insulator damascene and various combinations of the above methods. The lift-off and thru-mask methods are more valuable for large features like those typically encountered in chip packaging. Unlike the lift-off and the thru-mask methods, the metal RIE and damascene methods have been the process of choice for chip metallizations where the ground rules are typically below one micron.
In the damascene process, metal film is deposited over the entire patterned substrate surfaces to fill trenches and vias. This is then followed by metal planarization to remove metal overburden and isolate and define the wiring pattern. When metal deposition is by electroplating or by electroless process, the plating is preceded by the deposition of a plating base or seed layer over the entire surface of the patterned wafer or substrate. Also, layers that may improve adhesion and prevent conductor/insulator interactions or interdiffusion are deposited between the plating base or seed layer and the insulator.
In the metal RIE methods, blanket metal film is etched to define the conductor pattern. The gaps between the metal lines and vias are then filled with insulators. In high performance applications, the dielectric is planarized to define a flat metal level. One of the main advantages of the damascene process as compared to metal RIE is that it is often easier to etch an insulator as opposed to metal. Also, insulator gap fill and planarization may be more problematic. However, the last wiring level, referred to as Mlast, may not require a planar metal/insulator layer and typically is of a less dense pitch. Accordingly, the use of a damascene process may not provide a significant advantage for the last wiring level because of low thruput of the CMP step.
Moreover, this last wiring level typically contains very wide metal lines for power bussing and large pads for wirebonds or C4 solder balls. For the chemical-mechanical polishing (CMP) process, these relatively large metal structures are sensitive to dishing (see FIG. 1). Also, erosion of the insulator adjacent to large metal feature is a source of yield loss, especially when they occur at lower levels.
It would be desirable to be able to employ a process incorporating a subtractive etch or sub-etch method, for instance, thru-mask plating for depositing the metal features on a suitable seed layer. However, the most difficult aspect of the thru-mask process is the seed layer etching step.
In chip packaging wiring dimensions, the features of interest are about 5 to 30 microns in depth and about 40 to 200 microns in lateral dimensions. The plating base or seed layer are typically about 200 to 600 nm thick. Hence the loss of 500 nm in a 50-100 micron feature is not detrimental to yield or performance.
In sharp contrast to packaging features, in chip interconnection upper metal levels, the dimensions of interest are about 500-3000 nm in depth. The seed layer must be thinner than those used in packaging, typically about 30-100 nm. However, during the seed layer etching step, because the metal etching step tends to be isotropic, the profile of structures with smaller dimensions (submicron) are more degraded than their larger counterparts, as illustrated in FIG. 2. The loss of 100 nm in a 700 nm interconnection structure is a detrimental ground rule violation (see FIG. 2). Therefore, for such thru-mask method to be effective in chip wiring, particularly in the sub-micron regime, it is imperative to provide a method for removing the seed layer without significantly distorting the profile of the plated structures of interest.